1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a parallel test circuit for testing memory devices.
2. Description of the Related Art
The ever increasing complexity of semiconductor components has been matched, in recent years, by similar developments in test and reliability philosophies and practices.
Historically, semiconductor memory testing was performed for a variety of reasons. Memory manufacturers perform tests to guarantee performance within predefined specifications and to screen out those components not meeting the specification.
Generally a plurality of memory cells are fabricated on a wafer, and then separated so as to be subjected to a packaging process. A self-test circuit, provided within the semiconductor memory device, has been used to evaluate the performance of memory cells.
The test of semiconductor memory devices is generally performed in two steps. The first step is performed in what is known as a wafer state (hereinafter referred to as wafer test), and the second step in what is known as a package state (hereinafter referred to as package test).
The wafer test is performed before separating the memory cells fabricated on the wafer to detect defective memory cells. An external detection terminal is directly coupled to each output pad of the test circuit which is provided in the memory device and fabricated on the wafer. Accordingly, defective cells are either removed or repaired.
After successful completion of the wafer test, memory cells are then subjected to a packaging process to generate an assembled final product. The package test is performed after the packaging process in order to remove those defective memory cells produced during the packaging process.
Because input/output pins of the memory device are connected to an output pad associated with a test circuit, a test board is generally used to connect such input/output pins to external detection terminals when performing the package test. Ordinarily, both wafer and package tests use a parallel test procedure which enables a plurality of memory cells to be tested simultaneously. Parallel test modes and practices are known, and have been described in some detail in "Semiconductor Memories: A Handbook of Design, Manufacture, and Application" 2nd Ed., by Betty Prince; John Wiley & Sons, pp. 698-717 (1991).
FIG. 2 schematically shows a conventional 16-bit parallel test circuit such as may be found in a 2 Mbyte.times.8 (i.e., 16 Mbit) dynamic random access memory (DRAM). A data output path is provided having 16 accessible data lines DBi/ DBi (where i=0 to 15), eight 2-bit comparators, a .phi.FTE signal input, 8 output buffers, and 8 output pads. FIG. 1 illustrates a conventional operational timing chart showing the relationship of parallel test enable signal .phi.FTE (a controlling input to the parallel test circuit in FIG. 2) as a function of DRAM read/write control signals WE, CAS and RAS.
When row address strobe signal RAS transits from a logic `high` state to a logic `low` state, as would be the case after both column address strobe signal CAS and write enable signal WE are triggered logic `low`, then parallel test signal .phi.FTE is triggered logic `high` from a logic `low` state. In this condition, test data output from memory cells is input, in parallel, to eight 2-bit comparators to perform an appropriate wafer or package test. Hence, parallel test enable signal .phi.FTE serves as an enable control signal for the 2-bit comparators. Output signals from each of the comparators are transferred via output buffers to a corresponding output pad.
FIG. 3 shows a possible logic circuit of each of the 2-bit comparators shown in FIG. 2. As provided, each 2-bit comparator includes a first set of NAND gates and a second set of NOR gates. For this example, when input signals DB0 and DB1 are both at the same logic level, an output signal Dcom therefrom will be generated having a logic `high` level. Conversely, when input signals DB0 and DB1 are not the same logic level, output signal Dcom will be at logic `low` level. This provides a way to test for defective cells in a memory cell array quickly and accurately.
In the conventional test circuit of FIG. 2, test results will appear along the output pads of the memory device under test (during both the wafer and package tests). The test results at all output pads must necessarily be evaluated. Immediately after a wafer test, defective cells can be repaired if the addresses of defective cells are identifiable.
The entire operation of a memory device is tested again during the package test. This proves unnecessary and redundant. Nevertheless, test results at all available output pads are recorded and evaluated because test results are distributed over all output pads.
As a result, when a number of packages are subjected to a simultaneous parallel test, the number of memory cells that can be tested simultaneously, is in effect severely limited. Consequently, test costs increase as a result of too great a test time.